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| EM MICROELECTRONIC-MARIN SA V6108 40 Segment Static LCD Driver Features n Serial data input / output n Low dynamic current, 5 A max. n Low standby current, 1 A max. n Separate input and display voltages n Wide power supply range: VDD (logic) 2 to 8 V, VLCD (display) VDD to 12 V n On-chip latches separate control and display sections n Drives up to 40 LCD segments in direct drive n Crossfree cascadable n Schmitt Trigger on the inputs n 30 ns (typ.) glitch filter on every input n High noise immunity n Segment outputs short circuit protected n LCD blanking function n - 40 to +85 OC temperature range n On request extended temperature range, - 40 to +125 OC n QFP52 and TAB packages Typical Operating Configuration SEG 41- 80 V6108 V6108 Description The V 6108 is a CMOS integrated circuit that drives LCD. The circuit drives up to 40 LCD segments from a serial clocked input. It has a serial output for cascading to further drives. The serially clocked data is parallel loaded into 40 latches under control of the strobe pin. The latched data determines which segments are ON or OFF. Any segment output can be used to drive a backplane. A blank function is provided to clear the display. STR Applications n n n n n n n Balances and scales Automotive displays Utility meters Large displays Pagers Portable, battery operated products Telephones QFP52 1 V6108 1 V6108 Absolute Maximum Ratings -0.3V to +10V VDD -0.3V to +14V VLCD VLOGIC -0.3V to VDD+0.3V VDISP TSTO PMAX VSmax TS 1) Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level. - 65 to +150 C 100 mW 1000V o 250 C x 10 s VDD to VLCD + 0.3V o Operating Conditions Parameter Operating temperature Logic supply voltage LCD supply voltage 1) 1) Symbol Min. Typ. Max. Units TA VDD -40 2.0 VDD +125 8 12 O VLCD has to be higher or equal to VDD Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. C V V The maximum operating temperature is confirmed Table 2 by sampling at initial device qualification. In production, all devices are tested at +85 oC. On o request devices tested at+125 C can be supplied. Electrical Characteristics IDD ILCD IDD ILCD VIL VIH IIL VOH VOL VSH VSL ISC 1) 2) See note 1) See note See note 1)2) See note 1)3) 1) 0.1 0.1 55 1 1 5 75 0.8 0.6 A A A A V V A mV mV mV mV mA Table 3 VIN =VSS or VIN =VDD IH = 100 A VDD = VLCD = 4.5 V IL = 100 A VDD = VLCD = 4.5 V IH = 20 A, VDD = VLCD = 4.5 V IL = 20 A, VDD = VLCD = 4.5 V 3.8 3.5 1 VDD - 100 VLCD- 100 VSS + 100 VSS + 100 Tested with VIL= VSS, VIH= VDD Tested with fCL = 100 kHz, FDI= 50 kHz, 50 pF on each segment 3) Tested with fFL = 64 Hz, fCL= 0 Hz, 50 pF on each segment Timing Characteristics Parameter VDD = 5V 10%, VLCD = 12 V and TA = -40 to +85oC, unless otherwise specified Symbol Test Conditions tCH tCL tCR tCF tDS tDH tPD tP tD tSTR fFR tSF tSR Min. 500 500 250 0 50 250 200 Typ. Max. 500 500 Units ns ns ns ns ns ns ns ns ns ns MHz s s Clock high pulse width Clock low pulse width Clock and FR rise time Clock and FR fall time Data input setup time Data input hold time Data output propagation CLK falling to STR rising STR falling to CLK falling STR pulse width FR frequency Delay S1 - S40 fall time Delay S1 - S40 rise time 1) Recommended frame frequency. CLOAD = 50 pF 600 800 64 Hz 0.5 2.9 1) 1 1 5 2) 2) Maximum test frequency. Table 4 2 V6108 tCR 3 V6108 4 V6108 100 90 80 70 60 50 40 30 20 10 0 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 VDD CLK DI Shift Register 40 Bits DO S1...S40 VLCD VDD FR DI DO CLK STR R VSS 40 Latches STR Functional Description AC Table 5 Supply Voltages VLCD, VDD, VSS VDD is the positive supply line for the logic and VLCD for the display signals. VLCD has to be equal or higher than VDD. All voltages are specified relative to VSS. LS 2) FR LS 2) Data Input / Output (DI / DO) The data input pin (Dl) accepts serial data from the data source. The data is clocked in a rate determined by the clock input frequency (CLK). A logic "1" on Dl corresponds to a visible segment when the backplane is driven by a signal corresponding to logic "0". The data at DO is equal to the data at Dl delayed by 40 clock periods. In VSS SEG F = Noise Filter 2) LS = Voltage Level Shifter 1) SEG 40 Fig. 8 5 V6108 order to cascade devices the DO of one chip must be connected to Dl of the following chip (see Fig. 1). Segment Driver The number of segment drivers available on the chip is 40. Each segment driver can be used as backplane-driver. If two or more drivers are connected together, care must be taken to ensure the drivers do not cause circuit malfunction by driving one against the other. CLK Input The clock input pin (CLK) is used to clock the Dl serial data into the 40-bit shift register. Loading, shifting and outputting of the data occurs at the falling edge of this clock (see Fig. 3). When cascading devices, all CLK lines should be tied together. FR Input This input controls the segment output switching frequency according to Table 6. It must be connected to an external clock signal. When cascading devices, their FR inputs may all be connected to a common signal. STR Input The strobe input pin (STR) is used to latch the input data shifted into the 40-bit shift register. The latched data is held for display. A logic "1" on the STR input transfers the data contained in the shift register cells to the corresponding latches. The latches remain open during the whole time STR remains at logic "1". When cascading devices the STR lines should all be connected. Segment Switching Table Latched Signal (DI) 0 = VIL 1 = VIH 0 0 1 1 Signal FR 0 1 0 1 Segment Voltage 0 = VSS 1 = VLCD 0 1 1 0 Table 6 R Input When R is active (high), the display is blanked: all segment outputs are tied to VSS. R does not clear the information in the latches. V 6108 V 6108 6 V6108 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 R FR STR CLK DO VLCD VSS VDD S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 R FR STR CLK DO VLCD VSS VDD V6108 V6108 Package and Ordering Information The V 6108 is available in the following packages: QFP52, pin plastic package TAB, tape automated bonding Chip form V6108 52F V6108 TAB V6108 Chip * When ordering, please specify the complete part number and package. * on request EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin product. EM Microelectronic-Marin reserves the right to change circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version. (c) 1997 EM Microelectronic-Marin SA, 09/97, Rev. B/157 8 |
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